Sr Staff Engineer, SoC RTL Design
Core
Define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads.
Role type
Staff Digital Design Engineer (SoC RTL)
Builds
Custom IP blocks and SoC components for AI chips
Domain
Semiconductor / AI Hardware / RISC-V
Deliverable
production ML models
Required skills
RTL development (Verilog/VHDL), computer architecture, IP microarchitecture, PPA optimization, ASIC flows, synthesis, timing closure
Preferred skills
on-chip fabric design, interconnect design, validation (emulation, FPGA, UVM)
Technologies
Verilog, VHDL, UVM, FPGA
Responsibilities
Architecture and RTL implementation of custom IP blocks and SoC components; Performance-aware design decisions for compute, interconnect, or memory-heavy blocks; Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows; Strong synthesis and timing closure awareness to support backend teams
Seniority
Staff, hands-on IC
