Sr EDA Engineer
Core
Maintain, support, and enhance production RTL-to-Gates implementation, static verification, and signoff flows for digital backend projects.
Role type
Senior IC EDA flow engineer (RTL-to-Gates & Signoff)
Builds
Production-quality RTL-to-Gates implementation flows and static verification/signoff infrastructure
Domain
Semiconductor EDA / Digital Backend Implementation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-Gates implementation, Static timing analysis, Power analysis, Lint/CDC/RDC static checks, Tcl scripting, Python scripting, Perl scripting, SDC creation, Timing constraint development, UPF/CPF low-power concepts, Hierarchical SoC design, QoR optimization
Preferred skills
Synopsys tools expertise, Flow migration experience, Cross-site coordination
Technologies
Synopsys, Tcl, Python, Perl, SDC, UPF, CPF
Responsibilities
Develop and debug flow infrastructure using industry-standard EDA tools; Investigate and resolve user issues to ensure robust flow operation; Contribute to automation enhancements and reporting standardization; Support flow migration to next-generation platforms including porting scripts and validating migrated flows; Collaborate with global teams to deploy best practices and ensure consistency across projects.
Seniority
Senior, hands-on IC
