ASIC Verification Engineering
1,763 open positions
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SYSTEM VIRTUAL PLATFORM DEVELOPER EricssonAustin,Texas,United States 21d Develop and integrate Transaction Level Models (TLMs) in SystemC/C++ to create virtual SoCs for pre-silicon software development and validation of 5G/6G network products.
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Design Verification Engineer AppleHerzliya, Israel 21d Develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors for large-scale SoCs.
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Senior Physical Verification Engineer NVIDIAIsrael, Tel Aviv 21d Lead signoff-quality verification for advanced silicon programs, driving physical verification strategy and closure for complex designs to achieve tapeout readiness.
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Senior Staff, Emulation Engineer MarvellBangalore, IN 21d Develop and maintain emulation models, test plans, and debug flows for connectivity silicon (Optical DSPs, Ethernet PHYs, AEC/AOC) to bridge RTL design and real-world system behavior before tape-out.
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Senior ASIC Design Verification Engineer - Slingshot HpeChippewa Falls, Wisconsin, United States of America $147k–$279k21d Lead pre-silicon design verification for ASICs using SystemVerilog and UVM, developing testbenches, scoreboards, and coverage strategies to ensure functional correctness before silicon fabrication.
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ASIC Verification Engineer CiscoTaipei, Taiwan 21d Developing test benches and verification infrastructure for next-generation programmable ASICs used in high-speed packet forwarding and switching systems.
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Principal Engineer - Design Verification Renesas-ElectronicsHyderabad, TS, in 22d Lead verification R&D for advanced microcontrollers and microprocessors, ensuring products work correctly, safely, and securely through test plan creation, coverage closure, and gate-level simulation.
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Lead DFT Engineer Advanced Micro Devices, IncBangalore, India 22d Lead DFT Engineer implementing and verifying DFT architecture, scan insertion, ATPG pattern generation, and test coverage analysis for cutting-edge processor designs.
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Senior CAD Engineer – Physical Verification MicronBoise, Idaho, United States of America 22d Develop and maintain physical verification tools, flows, and methodologies for DRAM, HBM, NAND, and emerging memory products.
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CPU Software Intern for Verification ArmSophia Antipolis, France €27k22d Support verification of Arm Cortex IPs and develop scripts/tools for CI flow and templating languages.
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Digital Verification Senior Manager NxpShanghai (Pudong), CN 22d Lead an SoC verification team developing advanced MPU and MCU products, owning strategy, planning, execution, and sign-off.
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ASICS Design Verification Engineer-Senior QualcommSan Diego, California, United States of America $122k–$183k22d Develop comprehensive pre-silicon test planning, testbench development, coverage, assertion models, and formal verification for digital power IP within the ASIC verification lifecycle.
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Design Verification Engineer Siemens-EdaNew Cairo, EGY, Egypt $24k22d Develop and execute verification plans, design simulation/co-emulation environments, and debug hardware/software DUTs for storage solutions.
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Staff Engineer, Design Verification Engineering AnalogdevicesIndia, Bangalore, RMZ 22d Architect and lead verification strategies for complex analog and mixed-signal semiconductor designs, ensuring product quality and reliability.
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Design-for-Test (DFT) Engineer – High-Performance CPU (New Grad) MediaTekAustin, TX 22d Define and implement DFT architectures for high-performance CPU subsystems, generate and simulate test patterns, and support post-silicon validation.
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FPGA Design Engineer SQUARE ONE RESOURCES sp. z o.o.Warszawa, mazowieckie 23d Develop verification environments and perform functional verification for FPGA-based products.
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IC Verification Engineer BroadcomIND-Bangalore Electronic City - S1, IN 23d Build test plans, functional coverage, and scalable test benches for Block/Core/SoC verification using System Verilog and UVM.
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GPU Design Verification Engineer↗ AMDMarkham, Ontario, Canada 24d GPU Design Verification Engineer responsible for achieving functional and performance closure on digital design blocks within Graphics Core IP (GFXIP) using advanced verification methodologies and AI-driven workflows.
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Senior Design Verification Engineer MicrosoftUnited States, Washington, Redmond 25d Lead pre-silicon verification and post-silicon validation for custom Intellectual Property (IP) components, defining strategies and executing end-to-end verification plans at block, sub-system, or system levels.
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