Senior Engineer-ASIC Design Verification
Core
Senior ASIC Design Verification Engineer responsible for IP/Block and sub-system verification from test plan creation to signoff, ensuring first-pass product quality through multi-dimensional coverage.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Memory and storage solutions (DRAM, NAND, NOR) for data centers, AI, 5G, and mobile applications
Domain
Semiconductor / Memory and Storage / ASIC Design
Required skills
SystemVerilog/UVM, AMBA protocols (APB/AHB/AXI), RTL debugging, functional coverage coding, assertions, mixed-mode verification
Preferred skills
Mentoring junior engineers, cross-functional collaboration, AI tool utilization
Technologies
SystemVerilog, UVM, Verilog, AMBA (APB/AHB/AXI)
Responsibilities
Create test plans and develop UVM environments/testbenches; Ensure verification coverage including mixed-mode; Debug RTL and analyze code coverage; Mentor junior team members
Seniority
Senior, hands-on IC
