ASIC Design Verification Engineer
Core
Senior Verification Engineer developing ASICs for next-generation switching systems and programmable packet forwarding.
Role type
Senior IC ASIC Design Verification Engineer
Builds
ASICs for Cisco Nexus and ACI switching systems
Domain
Networking hardware / ASIC design
Required skills
System Verilog, UVM methodology, C++, Python scripting, functional coverage, constrained random DV environments, high-speed Ethernet protocols, simulation, emulation, ASIC bring-up
Preferred skills
Perl scripting, TCL, shell programming, C programming
Technologies
System Verilog, UVM, Python, Perl, TCL, shell, C, C++, OpenStack, Docker, Open vSwitch
Responsibilities
Designing UVM/SystemVerilog testbenches, defining new DV methodologies, enhancing existing testbenches, end-to-end verification of design blocks, top-level verification, emulation testing, ASIC bring-up
Seniority
Senior, hands-on IC
