ASIC Verification Engineering
934 open positions
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PRINCIPAL ENGINEER, DDEG DESIGN METHOD MicronHyderabad, Telangana, India 1mo Lead verification and end-to-end analysis for sophisticated full-chip gate-level custom designs in advanced low-power and power management technologies (DDR4, LPDDR4, DDR5, LPDDR5) operating at high speeds up to 6400MT/s.
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Verification Engineer
AmazonTel Aviv-Yafo, Tel Aviv, Israel
1mo
Pre-silicon verification engineer developing a revolutionary semiconductor platform for AWS cloud customers.
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ASIC VERIFICATION ENGINEER BroadcomIND-Bangalore Electronic City - S1 1mo Develop and maintain verification environments for cutting-edge CSG Switches and AI Network Infrastructure using SystemVerilog/UVM.
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IC Verification Engineer AumovioBengaluru, KA, in 1mo Develop functional models for Analog and/or Digital IPs, create test benches, and perform functional verification for ICs (ASICs) to ensure optimum verification coverage and quality.
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Digital IC Verification Engineer (New Grad) MonolithicpowerHong Kong - China 1mo Perform functional and system-level verification of digital and mixed-signal chips using advanced methodologies and ASIC tools.
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Senior Verification Manager, SERDES PHY↗ Synopsys IncMississauga, Ontario, Canada 1mo Lead verification for flagship SERDES PHY IP powering high-performance SoCs, ensuring sign-off quality for automotive, data center, and AI markets.
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SOC Verification Engineer NVIDIAIndia, Bengaluru 1mo Verify CPU, GPU, high-speed interfaces, Design for Debug, and horizontal functions like Boot and Power management at subsystem or full chip testbenches including FPGA/Silicon.
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Senior Lead Engineer - FPGA↗ Collins AerospaceKA, IN 1mo Lead verification planning, execution, and reviews for high-assurance airborne electronic hardware in compliance with DO-254 standards.
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Senior FPGA Design Engineer AlteraBengaluru, Karnataka, India 1mo Develop FPGA-based solutions for pre-silicon validation, hardware prototyping, and high-speed interface verification to accelerate product development.
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ASIC/FPGA Design Verification Engineer, Senior Staff↗ QualcommOttawa, ON, CA 1mo Lead ASIC/FPGA design verification for high-performance, low-power IP blocks and subsystems (PCIe Gen7, CXL 4.0) using SystemVerilog and UVM.
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SoC DFT Engineer, Cloud↗
GoogleSunnyvale, CA, US
$163k–$163k1mo
Define, implement, and deploy advanced Design-for-Test (DFT) methodologies for next-generation System-on-Chip (SoC) architectures, specifically focusing on TPU (Tensor Processing Unit) hardware for AI/ML acceleration.
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MTS Silicon Design Engineer↗ AMDSanta Clara, CA, US 1mo Research, design, develop, and test electronic components and systems for semiconductor manufacturing, focusing on verification and debugging of new features.
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IC Verification Engineer↗ Xg Tech Pte. Ltd.Clementi, S00, SG 1mo Lead functional verification of complex IPs and SoCs to ensure high-quality, bug-free silicon for intelligent vehicle platforms.
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Lead DFT Engineer Enchargeai36Canada $200k–$200k1mo Architecting end-to-end Design for Test (DFT) strategies for complex SoCs to ensure manufacturability, reliability, and high test coverage for edge-to-cloud computing chips.
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Senior Formal Verification Engineer MicrosoftIndia, Karnataka, Bangalore 1mo Define and execute formal verification strategies for complex IPs, subsystems, and SoCs, developing plans based on architecture and microarchitecture specifications.
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Interface IP Verification Engineer (Pre-Silicon) - 18380↗ SynopsysAustin, TX, US $114k–$114k1mo Own verification of next-generation Interface IP (PCIe, CXL, DDR, Ethernet) powering AI, cloud, networking, and high-performance computing systems.
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Lead Application Engineer CadenceZHUBEI 01 1mo Lead Application Engineer specializing in AI-assisted verification solutions for digital design, IP, and SoC verification challenges.
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Physical Design Engineer - Physical Verification - Singapore↗ ByteDanceSingapore, S00, SG 1mo Own and drive Physical Verification (PV) signoff for advanced-node ASIC/SoC designs, managing the complete flow from PDK enablement through tapeout.
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[EMN] Senior IP Design Verification Engineer Bosch-GroupThành phố Hồ Chí Minh, Hồ Chí Minh, vn 1mo Own and execute Silicon IP based pre-silicon verifications (e.g., UCIe Interoperability) from planning through sign-off.
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Senior Analog Mixed Signal Verification Engineer↗ NXP SemiconductorsChandler, QC, CA 1mo Lead verification for automotive and industrial PMIC products from specification through signoff, ensuring functional correctness, safety, and robustness.
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Senior Analog Mixed Signal Verification Engineer NxpChandler (Office) 1mo Lead verification for automotive and industrial PMIC products from specification through signoff, ensuring functional correctness, safety, and robustness.
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DV engineer↗ Quest GlobalSan Jose, CA, US $156k–$156k1mo Leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects.
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CPU Emulation Engineer, Silicon↗
GoogleMountain View, CA, US
$163k–$163k1mo
Architect RTL partitioning, FPGA synthesis, and validation strategies for industry-standard emulation platforms to verify complex semiconductor IP blocks and full-chip designs.
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Director, Verification – US & Europe SilabsAustin $167k–$167k1mo Lead the Verification Organization for IP, Sub-system, and SoC verification, driving teams towards Gen-AI based verification methodologies.
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Senior ASIC Verification Engineer HpeSunnyvale, California, United States of America $154k–$154k1mo Senior ASIC Verification Engineer responsible for block-level and subsystem verification of high-speed networking chips, from test plan creation to coverage closure.
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Senior Design Verification Engineer↗ Micron TechnologyTlaquepaque, JAL, MX 1mo Develop and verify next-generation DRAM and emerging memory technologies for data centers, AI, automotive, and mobile applications.
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DFT Engineer
AmazonTel Aviv-Yafo, Tel Aviv, Israel
1mo
Design and implement advanced Design-for-Test (DFT) architectures for complex semiconductor platforms to ensure robust performance and support silicon bring-up.
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