ASIC Verification Engineering
1,763 open positions
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Senior System Verification Engineer NVIDIAUS, TX, Austin $200k25d Develop and implement RTL verification strategies and pre-silicon verification environments for NVIDIA's DGX server platform, focusing on board and system-level designs.
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Senior Engineer ASIC DV MicronHyderabad - Phoenix Aquila, India 25d Developing advanced verification components for complex IP designs using UVM methodologies and constrained random verification.
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Staff / Senior Staff Engineer Chip Verification InfineonSingapore 25d Execute end-to-end verification of complex System-on-Chip (SoC) designs, focusing on Network-on-Chip (NoC), interconnect, and system-level verification.
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Design Verification Engineer - APS Texas InstrumentsSanta Clara, CA, United States 25d Confirm accuracy of analog and mixed signal electronic designs before pattern generation/mask development and analyze equipment to establish operating data.
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Circuit Analysis and Modeling Engineer, Senior - Cork, Ireland↗ QualcommCork, County Cork, Ireland 25d Develop, verify, and release functional and behavioral models for custom memory IP used across Qualcomm's CPU portfolio.
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Verification Engineer Internship↗ ArquimeaMadrid, Community of Madrid, Spain 25d Electronic verification and FPGA development intern supporting firmware and embedded software teams in aerospace, defense, and security sectors.
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Senior SOC Design Engineer IntelMalaysia, Penang 25d Design and integrate microarchitecture, RTL logic, and verification environments for Intel's client chipsets and SoC products, ensuring functionality and performance of next-generation features.
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Foundation IP Design Verification Intern (Summer 2027) GlobalFoundriesUSA - California - Santa Clara 25d Support design verification for standard-cell libraries, memories, block-level IP, and chip-level integration using circuit simulation, formal verification, and AI-assisted methods.
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Digital Mixed-Signal Modeling Engineer AppleSunnyvale, United States of America 25d Develop behavioral models and verification infrastructure for Analog/RF/Mixed-Signal blocks and System-on-Chips (SoCs) to ensure pre-silicon validation and emulation readiness.
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DFT Architect Advanced Micro Devices, IncBangalore, India 26d Ensure testability and manufacturing quality of next-generation EPYC Server SoCs through DFT implementation, ATPG, and LBIST.
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IP Verification Engineer EricssonAustin,Texas,United States 26d Senior Design Verification Engineer building and validating RTL blocks for Ericsson's 5G ASIC IP, ensuring silicon reliability for global 5G infrastructure.
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Foundation IP Memory Verification Engineer↗ Avago Technologies International Sales Pte. LimitedYishun, S00, SG 26d Design engineer developing foundation IP for AI products, focusing on memory compilers, logic cells, and custom macros using advanced process technology.
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Staff / Senior Staff Engineer Chip Verification↗ Infineon TechnologiesSG 26d Execute end-to-end verification of complex System-on-Chip (SoC) designs, focusing on Network-on-Chip (NoC), interconnect, and system-level verification.
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Principal Analog Mixed-Signal Design Verification Engineer Blue OriginKraków, małopolskie 26d Lead mixed-mode design verification methodology, define co-simulation EDA environments, and develop models for complex System-on-Chip (SoC) simulation to support space-based connectivity systems.
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Senior Engineer, Design Verification (MCU) Renesas-ElectronicsBengaluru, KA, in 27d End-to-end verification execution for SoCs owning complex digital IP's and subsystems, from specification to sign-off.
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Principal SOC Performance Verification Engineer MicrosoftIndia, Karnataka, Bangalore 27d Pre-silicon SoC performance verification engineer responsible for developing strategies, test plans, and environments to validate power and performance tradeoffs across CPU, fabric, and memory subsystems.
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Design Verification Technical Manager (High-Speed IO: PCIe & USB) MediaTekHsinChu 27d Architect and execute comprehensive verification strategies for next-generation high-performance SoCs, focusing on IP-level and subsystem-level verification for mission-critical high-speed serial protocols (PCIe and USB).
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