ASIC Verification Engineering
935 open positions
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Functional Verification Engineer AccentureBengaluru 1mo Develop and execute comprehensive testbenches to verify the functional correctness and protocol compliance of USB digital designs at the block and system level.
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Principal Digital Engineer Renesas-ElectronicsAustin, TEXAS, us 1mo Define scalable verification and validation methodologies for advanced digital power management products used in AI, datacenter, and high-performance computing applications.
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Senior Verification Engineer MicrosoftUnited States, California, Mountain View 1mo Lead pre-silicon verification for custom IP and subsystem components in AI SoCs, ensuring architectural and micro-architectural intent is met.
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ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years CiscoBangalore, India 1mo Lead Design-for-Test (DFT) implementation for complex ASICs in Cisco's Silicon One architecture, ensuring testability and debug capabilities for switching, routing, and wireless hardware.
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Principal Engineer, Design Verification MarvellHo Chi Minh $0k–$0k1mo Verify circuitry for innovative storage technologies including ultra-fast read channels, high-performance processors, and transceivers for HDD and SSD electronics markets.
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Staff Engineer - CPU Verification SifiveHyderabad, India 1mo Define verification strategies and develop scalable testbenches for CPU sub-systems (Load/Store units, MMUs, Execution Pipelines) to ensure architectural correctness.
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Design Verification Architect↗ Intel CorporationFolsom, CA, US $164k–$232k1mo Defines, architects, and documents verification strategy and methodologies for implementing and verifying pre-silicon design; architects testbenches using UVM or formal-based approaches.
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Lead Software Engineer: Jasper R&D↗ Cadence Design SystemsBelo Horizonte, MG, BR 1mo Lead Software Engineer for Jasper Clock Domain Crossing (CDC) team, focusing on testing, validating, and deploying enhancements for a formal verification tool.
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Senior Front-End Infrastructure Engineer↗ Prodapt SolutionsSan Jose, CA, US 1mo Design, support, and optimize front-end verification flows and CAD infrastructure for large-scale SoC/ASIC projects.
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Design Verification Engineer AlteraRegus, Madhapur 1mo Develops, validates, and debugs software abstractions and frameworks for FPGA acceleration to support embedded, data center, and communication clients.
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CPU Core Design Verification Engineer↗ AMDAustin, TX, US 1mo Verify new and existing microarchitectural features in AMD's next-generation x86 CPU cores using C++ and Verilog/SystemVerilog.
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Staff PCIe Verification Engineer↗ ArmToronto, ON, CA $159k–$159k1mo Verify functionality and performance of High Speed IOs (PCIe, CXL) at the Sub-system level for next-generation SoCs.
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Senior Verification Engineer AnalogdevicesUS, MA, Wilmington $110k–$110k1mo Own verification efforts for complex security IP and subsystem designs, ensuring robust functionality and security across hardware solutions.
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Sr. Design for Test (DFT) Engineer↗ LightmatterToronto, ON, CA 1mo Design for Test (DFT) insertion, test pattern generation, and post-silicon bring-up for high-performance ASICs in leading-edge CMOS technology.
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Senior AMS Verification leader NxpMilan $61k–$61k1mo Lead mixed-signal verification activities for advanced automotive and industrial power management products, defining strategies and ensuring robust silicon delivery.
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Staff/ Principal Design Verification Engineer AsteralabsTel Aviv 1mo Develop ASIC verification environments and testbenches to validate high-performance digital blocks, subsystems, and full-chip designs for next-generation AI connectivity silicon.
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AMS Verification Engineer (all gender) AltenRemote 2mo AMS verification of I/O interfaces, defining verification strategies, developing testbenches, executing simulations, and debugging functional, electrical, and timing issues.
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Sr Principal Design Engineer CadenceSAN JOSE $154k–$154k2mo Senior Solutions Engineer developing hardware emulation and FPGA prototyping platforms for semiconductor customers, bridging R&D and customer needs to solve complex high-speed protocol challenges.
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CPU Verification Engineer IntelUS, Texas, Austin $106k–$106k2mo Develop and execute verification plans to validate CPU logic against architectural specifications for next-generation processors.
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ASIC Verification Engineer BroadcomUSA-CA Irvine Alton Parkway Bldg 2 $101k–$101k2mo Develop verification environments and testbench components for high-speed interconnect ASICs (100Gbps to 400Gbps) using SystemVerilog UVM, collaborating with architecture and firmware teams.
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GPU Verification Engineer - New College Grad 2026 NVIDIAUS, MA, Westford $100k–$167k2mo Verify ASIC design, architecture, and micro-architecture of NVIDIA GPUs and SoCs using sophisticated verification methodologies.
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FPGA Engineer Sapsol-Technologies-IncMelbourne, Florida, United States 2mo Develop RTL designs, verification environments, and hardware lifecycle management for FPGA/ASIC products.
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Senior Staff Engineer, GPU Design Verification (Subsystems) Samsung Electronics3655 N 1st St, San Jose, CA, USA $180k–$180k2mo Senior Staff Engineer responsible for verification strategy and hands-on validation of complex GPU subsystems for next-generation mobile GPUs, ensuring functional correctness and performance integrity.
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Senior/ IC Design Engineer (Design Verification)↗ Aurexis Tech Pte. Ltd.Singapore, S00, SG 2mo Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs, building SystemVerilog/UVM environments and driving verification closure.
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Principal Modem PHY IP Design Verification Engineer - Terawave BlueoriginCentral Texas, US $269k–$269k2mo Lead verification of advanced modem PHY IP for next-generation wireless ASIC platforms within the Terawave satellite communications network.
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CPU Verification Engineer, Verification Team
AmazonHaifa, Haifa, Israel
2mo
Verifying the correctness, performance, and robustness of next-generation ARM CPU cores and their surrounding subsystems before silicon production.
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Staff Verification Design Engineer, DRAM MicronBoise, ID - Main Site 2mo Design and drive verification strategies for Micron's leading-edge DRAM memory products, ensuring performance, quality, and reliability from gate-level to full chip.
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