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Hardware & Physical Engineering
› ASIC Verification Engineering
ASIC Verification Engineering
1,768 open positions
Hardware Design Verification Engineer
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European Tech Recruit
Cork, County Cork, Ireland
15d
Security Hardware Design Verification Engineer developing and verifying complex security subsystems (root of trust, cryptographic accelerators) for next-generation SoCs.
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Design Verification Engineer
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Lancesoft, Inc.
Markham, Ontario, Canada
15d
Functional verification of complex ASICs and IP cores for CPU/GPU development.
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Senior AMS DV Engineer
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Analog Devices
Valencia, Valencian Community, Spain
€43k
15d
Senior Analog Mixed Signal (AMS) Design Verification Engineer developing verification strategies and testbenches for portable consumer applications.
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Senior AMS Verification Engineer
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IC Resources
Remote
15d
Senior AMS Verification Engineer developing Real-Number models and testbenches for analog and mixed-signal IPs/blocks to ensure consistency with schematics.
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Verification Engineer, Senior
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Qualcomm
Toronto, ON, CA
$108k–$158k
15d
Senior ASIC verification engineer defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) for high-performance, low-power products.
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Senior Chip Design Verification Engineer
NVIDIA
Israel, Tel Aviv
15d
Verifying front-end Switch silicon design blocks to specifications with a focus on power, area, and performance.
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Lead Product Engineer
Cadence
SHANGHAI, CN
15d
Lead Product Engineer driving Cadence SoC Verification solutions (Simulation, SVG SW) for customers, including deploying Xcelium and USB VIP technologies in China.
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Embedded Systems and IP Engineer
Altera
Penang 15, Penang, Malaysia
15d
Design, implement, verify, and release configurable soft IP and embedded solutions for FPGA devices, bridging hardware, firmware, and software boundaries.
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Embedded Systems and IP Engineer
Altera
Penang 15, Penang, Malaysia
15d
Design, implement, verify, and release configurable soft IP and embedded solutions for FPGA devices, bridging hardware, firmware, and software boundaries.
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New College Grad - HBM VERIFICATION
Micron
Jalisco, Mexico
15d
Provide verification support for pre-silicon full chip designs and develop test benches for HBM and emerging memory architectures.
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Senior Verification Engineer - CPU
NVIDIA
US, CA, Santa Clara
$168k–$265k
15d
Define, plan, and execute verification strategies for sophisticated CPU designs, ensuring high-quality product delivery from consumer graphics to AI and self-driving vehicles.
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CPU Design Verification Sr Lead Engineer
Qualcomm
Hyderabad, Telangāna, India
15d
Lead verification engineer for high-performance, low-power CPUs, focusing on power management and system validation.
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Senior GPU DV Engineer
Qualcomm
San Diego, California, United States of America
15d
Architect, design, implement, verify, and optimize performance and power of GPU cores and Graphics IP.
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NCG Digital Design Engineer
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Micron Technology
Tlaquepaque, JAL, MX
15d
Develop and verify advanced digital and mixed-signal circuits and Memory/Logic IP for next-generation memory products using simulation, modeling, and AI-assisted tools.
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Senior Chip Design Verification Engineer
NVIDIA
Israel, Tel Aviv
15d
Verifying front-end design for Switch silicon, focusing on power, area, and performance constraints.
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DRAM Verification Engineer, Up to Sr. Staff
Qualcomm
Hsinchu City, Taiwan
15d
Develop and verify next-generation custom DRAM and memory subsystem solutions, ensuring functional correctness, performance, and robust verification closure.
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Verification Engineer, Senior
Qualcomm
Toronto, Ontario, Canada
15d
Senior ASIC verification engineer defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) for high-performance, low-power products.
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Pre-Silicon Digital Verification Engineer
Apple
Sunnyvale, United States of America
15d
Verifying complex digital IP blocks for mixed signal integrated circuits to ensure bug-free designs on the first tapeout.
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ASIC Design Verification Engineer I (Full Time) - United States
Cisco
San Jose, California, US
$95k–$157k
15d
Develop and verify ASICs for Cisco's core Switching, Routing, and Wireless products using simulation, emulation, and bring-up processes.
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MSIP Design Verification Engineer - Cork, Ireland
Qualcomm
Cork, Ireland
15d
Mixed-Signal Design Verification Engineer developing verification environments for SerDes, DDR, PLL, and other PHY IPs in next-generation Snapdragon SoCs.
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Senior Staff - Design Verification Engineer
TYLsemi
Bangalore, Karnataka
15d
Lead definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targeting AI, HPC, and Networking applications.
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SG Analog/Mixed-Signal Verification Engineer
Tetramem
Singapore
$80k–$180k
16d
Develop and implement mixed-signal verification and coverage plans for complex IC designs, design verification testbenches, and sign-off designs for tapeout.
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Staff Verification Engineer - CPU group
Arm
Cambridge, United Kingdom
16d
Build and refine simulation-focused verification environments for next-generation CPU IP, collaborating with design teams to ensure high-quality products for billions of devices.
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Sr . Principal Verification Engr
Nxp
Bangalore, IN
16d
Lead end-to-end pre-silicon System-on-Chip (SoC) verification, developing robust verification environments and driving silicon readiness.
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Principal Engineer, ASIC Validation
Micron
India
16d
Lead ASIC validation for complete SoC deployment on pre-silicon platforms using ZEBU emulation and Xilinx FPGA flows.
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DRAM Principal Design Verification Engineer
Micron
Boise, Idaho, United States of America
17d
Lead digital verification methodology and infrastructure development for next-generation DRAM products, driving scalable testbench architectures and AI-powered verification solutions.
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DRAM Principal Design Verification Engineer
Micron
Boise, ID - Main Site, US
17d
Lead digital verification methodology and infrastructure development for next-generation DRAM products, driving scalable testbench architectures and AI-powered verification solutions.
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Principal Engineer - Verification IP
Arm
Multiple locations
17d
Develop and maintain verification IP (VIP) tools for Arm Hardware IP products, specifically standard AMBA interface protocols, and drive their deployment into IP, Subsystem, or SoC test benches.
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Principal Firmware Development Engineer
Microsoft
United States, Washington, Redmond
17d
Lead system-level challenges and define architectural direction for SystemC/TLM-based virtual platforms supporting multiple generations of Azure silicon.
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Sr. Microprocessor Verification Engineer
Advanced Micro Devices, Inc
Fishkill, New York
17d
Senior verification engineer owning functional verification of high-performance Microprocessor designs from block level through full-chip integration.
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ASIC Verification Engineer, AI Networking IP
Advanced Micro Devices, Inc
OTTAWA, Canada
17d
Develop high-performance networking and communications IP for advanced AMD products by creating verification environments for leading edge AI networking silicon.
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AMS Design Verification Intern
Analog Devices
Assago, Provincia di Milano
17d
Intern role in Analog Mixed Signal (AMS) design verification, creating verification plans, modeling analog blocks, and managing UVM verification environments for high-precision ICs in display, lighting, and cloud power applications.
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RTL Design Engineer
Advanced Micro Devices, Inc
Hyderabad, India
18d
Design verification engineer developing and maintaining functional and performance tests for next-generation processor IP cores.
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Senior SOC Verification Engineer
Microsoft
India, Karnataka, Bangalore
18d
Pre-silicon SoC verification engineer responsible for developing verification strategies, test plans, environments, and tools to validate complex SoC architectures, data accelerators, and interconnect protocols.
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CPU Verification Engineer
Advanced Micro Devices, Inc
Bangalore, India
18d
Verification of power management features and system management functions for high-performance, ultralow-power x86 microprocessor cores.
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Senior Staff Formal Verification Engineer
Advanced Micro Devices, Inc
Penang, Malaysia
18d
Develop and maintain Formal Verification environments for next-generation AMD microprocessors (ASIC/SOC) powering gaming consoles, servers, PCs, and graphics cards.
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Verification Engineer - PCIE
NVIDIA
India, Bengaluru
18d
Verify ASIC design, architecture, golden models, and micro-architecture of PCI Express controllers at IP/sub-system levels for NVIDIA GPUs and SOCs.
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Senior Manager Digital Centric Verification (f/m/div)
Infineon
Belgrade
18d
Lead a team to deliver advanced digital verification work packages for mixed-signal contexts (AMS IPs and subsystems) within Infineon's business lines.
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Verification Engineer – AI SoC Development
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Intel Corporation
Toronto, ON, CA
CA$154k–CA$217k
18d
Build and configure emulation and FPGA models to accelerate RTL development and ensure robust hardware-software integration for Intel's next-generation SoC technologies.
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CPU Pre-Si Verification Sr Engineer
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Intel Corporation
Guadalajara, JAL, MX
18d
Develop and execute verification plans, test cases, and debug CPU designs to ensure functionality and performance.
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Principal Engineer - SOC Verification
Arm
Bengaluru, India
18d
Design Verification Engineer verifying complex Arm-based IPs, subsystems, and SoCs for next-generation computing platforms.
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CPU Verification Engineer, Up to Staff Level
Qualcomm
Hsinchu City, Taiwan
18d
Verify design features across all aspects of CPU using simulation, formal verification, emulation, and FPGA platforms.
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DDR Design Verification Lead Engineer
Qualcomm
Hyderabad, Telangāna, India
18d
Lead Design Verification (DV) engineer for LPDDR/DDR based IPs and Subsystems in the Infra IP team.
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ASIC Design Verification Engineer (Security Group) - Sr Staff
Qualcomm
Santa Clara, California, United States of America
18d
Sr Staff ASIC Design Verification Engineer developing and validating secure high-performance subsystems and SoC micro-architectures for Qualcomm products.
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Principal Physical Verification Engineer
Broadcom
USA-CA San Jose Innovation Drive
$144k
18d
Execute chip-level physical verification (DRC, LVS, ERC, PERC) and resolve issues for advanced node ASICs (3nm/2nm) and 2.5D/3D chiplet integration.
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Manager verification and validation
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Merlla Talent Hub
KA, IN
₹2500k–₹3500k
18d
Lead end-to-end Verification & Validation (V&V) activities for FPGA-based and electronic hardware systems in airborne safety-critical environments.
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Design Verification - Senior Staff Engineer/Mgr
Qualcomm
Hyderabad, Telangāna, India
18d
Senior Staff Engineer responsible for IP Level Verification of Qualcomm Spectra Camera Sub Systems Modules for next-gen products, ensuring enhanced features through end-to-end verification ownership.
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2027 Master Thesis Projects in ML Hardware Verification Lund
Arm
Lund, Sweden
SEK 60k
18d
Master's thesis projects focusing on hardware verification for neural accelerators, specifically developing AI-assisted workflows and graph-based analysis for coverage closure.
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Principal SoC Verification Engineer
Nxp
Austin (Oakhill, Office), US
18d
End-to-end ownership of verification planning, testbench development, execution, debug, and sign-off for next-generation automotive SoCs used in safety-critical applications.
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AMS Verif
Nxp
Sophia-Antipolis (Valbonne), FR
18d
Verification of complex Analog/Mixed-Signal (AMS) integrated circuits to ensure functionality, performance, and reliability.
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