Senior Staff, Emulation Engineer
Core
Develop and maintain emulation models, test plans, and debug flows for connectivity silicon (Optical DSPs, Ethernet PHYs, AEC/AOC) to bridge RTL design and real-world system behavior before tape-out.
Role type
Senior Staff Emulation Engineer (SoC/Hardware-Software Co-Validation)
Builds
Emulation models, test environments, and automation scripts for Palladium, Veloce, and Zebu platforms.
Domain
Semiconductor / Connectivity Silicon / Hardware Emulation
Required skills
SoC emulation model development, Verilog/SystemVerilog simulation and debug, emulation platform configuration (Palladium, Veloce, Zebu), HW/SW co-validation, scripting (Python, Perl, Tcl, UNIX shell), cross-functional collaboration
Preferred skills
Networking device emulation, mixed-signal design emulation, PHY/Layer-2/3 functionality, firmware/software bring-up, emulation infrastructure improvement
Technologies
Palladium, Veloce, Zebu, Verilog, SystemVerilog, Python, Perl, Tcl, UNIX shell
Responsibilities
Execute emulation model bring-up, test development, and debug for connectivity silicon programs; Implement platform configurations, transactors, speed bridges, and protocol adapters; Engage with EDA and emulation hardware vendors to resolve platform and tooling issues; Develop and maintain HW/SW enablement flows and scripts to support RTL validation; Collaborate with pre-silicon validation, design, firmware, and post-silicon teams to resolve bottlenecks; Build and maintain automation scripts and infrastructure to improve emulation environment productivity.
Seniority
Senior Staff, hands-on IC
