ASIC Verification Intern - Summer 2027
Core
Verify memory subsystem components in Tegra SOCs using industry standard methodologies to support consumer graphics, self-driving cars, HPC, cloud computing, and AI.
Role type
ASIC Verification Intern
Builds
Memory subsystem components for Tegra SOCs
Domain
Semiconductor / Hardware Design
Required skills
RTL design understanding, verification planning, debugging, formal verification, dynamic simulation, FPGA integration, post-silicon verification
Preferred skills
Verilog, SystemVerilog, UVM, C/C++/Java/Python/Perl, memory controllers, DDR protocols
Technologies
Tegra SOCs, FPGA, Linux, Windows, Verilog, SystemVerilog, UVM, C, C++, Java, Python, Perl
Responsibilities
Develop comprehensive verification plans for design changes, collaborate with RTL engineers to debug and close coverage, interact with performance teams for dynamic/formal verification, enable FPGA and software teams for testing, conduct post-silicon verification and debug
Seniority
Intern
