Senior Verification Engineer – High Speed Coherent Interconnect Hub
Core
Develop and maintain verification infrastructure for complex High Speed Coherent Interconnect Hub IP within NVIDIA's Tegra SoC, ensuring functional and performance signoff for multi-chip computing platforms.
Role type
Senior IC verification engineer (SoC/Interconnect)
Builds
High Speed Coherent Interconnect Hub IP for scalable, high-performance multi-chip computing platforms
Domain
Semiconductor / SoC Design / High-Speed Interconnects
Required skills
SystemVerilog, UVM, constrained-random verification, coverage-driven verification, RTL debugging, performance validation, protocol compliance verification, FPGA/emulation support, scripting (Python/Perl/Shell)
Preferred skills
High-speed coherent interconnect verification (CHI, AXI), NoC verification, cache coherency understanding, system-level data flow analysis, performance verification (bandwidth, latency, QoS)
Technologies
SystemVerilog, UVM, Python, Perl, Shell, FPGA, Emulation tools
Responsibilities
Develop and maintain verification infrastructure (testbenches, BFMs, checkers, monitors, scoreboards, assertions, constrained-random stimulus); Define and complete verification test plans for coherency, ordering, error handling, and performance; Verify protocol compliance and interoperability across SoC and multi-chip interfaces; Drive functional and code coverage closure; Debug complex RTL and verification issues; Collaborate with FPGA, emulation, software, and post-silicon teams for system validation and silicon bring-up
Seniority
Senior, hands-on IC
