Senior ASIC RTL Engineer
Core
Drive high-quality Design for Test (DFT) RTL to ensure robust and reliable silicon solutions for Cisco's core Switching, Routing, and Wireless products.
Role type
Senior ASIC RTL Engineer (DFT focus)
Builds
Advanced networking silicon aligned with Cisco Silicon One's scalable and flexible architecture
Domain
Semiconductor / Networking Hardware
Required skills
Verilog/System Verilog coding, front-end tools (simulators, linting, CDC checkers, synthesis, formal verification), industry standard interface protocols (AMBA AXI/APB/AHB, JTAG), memories
Preferred skills
Power optimization techniques, power intent (UPF), power estimation, DFT/MBIST, post-silicon debug
Technologies
Verilog, System Verilog, UPF, AMBA, JTAG
Responsibilities
Collaborate with Front-end RTL and backend physical design teams to gain deep understanding of chip architecture, drive high-quality DFT RTL, ensure robust and reliable silicon solutions meet Cisco's standards for performance and innovation
Seniority
Senior, hands-on IC
