Staff Functional Test Verification/Simulation Engineer
Core
Lead pre-silicon verification and simulation of next-generation Arm CPU/GPU architectures to ensure functional correctness and performance for billions of devices.
Role type
Staff IC functional test verification/simulation engineer
Builds
Scalable UVM/SystemVerilog testbenches, simulation flows, and pattern generation infrastructures for Arm CPU/GPU designs
Domain
Semiconductor hardware design (CPU/GPU) + SoC verification
Required skills
SystemVerilog, UVM, C/C++, Python scripting, RTL debugging, functional coverage analysis, EDA simulator usage
Preferred skills
AMBA protocols (CHI, AXI, AHB), power-aware verification, emulation, performance modeling
Technologies
Synopsys VCS, Cadence Xcelium/Palladium, Siemens Questa, Python
Responsibilities
Define verification strategies and target functional coverage for silicon; Port and execute functional/datapath/performance test cases; Design reusable testbenches and stimulus generation infrastructures; Build pattern generation flows and bridge pre-silicon simulation with post-silicon validation; Analyze functional coverage and debug complex multi-domain RTL/system-level issues
Seniority
Staff, hands-on IC with strategic scope
