Staff Structural Test Verification/Simulation Engineer
Core
Spearhead structural test, design-for-test (DFT), and test verification methodologies for advanced Arm products to ensure manufacturing test quality, high silicon yield, and robust fault coverage.
Role type
Staff IC structural test verification and simulation engineer
Builds
Pre-silicon verification strategies, ATPG/MBIST patterns, and silicon validation flows for advanced logic and memory architectures
Domain
Semiconductor / ASIC/SoC Design-for-Test
Required skills
ATPG pattern verification/simulation, MBIST pattern verification/simulation, ICL, PDL, Siemens Tessent, Synopsys TetraMAX, SystemVerilog/UVM, Python/Perl/Tcl scripting, silicon validation, yield debug
Preferred skills
Advanced process nodes (sub-7nm/5nm/3nm), low-power DFT, IJTAG (IEEE 1687), boundary-scan (IEEE 1149.1/4), cross-functional technical leadership
Technologies
ICL, PDL, Siemens Tessent, Synopsys TetraMAX, SystemVerilog, UVM, Python, Perl, Tcl
Responsibilities
Define pre-silicon verification and simulation strategy for advanced logic and memory test architectures, Drive simulation of ATPG patterns and logic diagnostics flows, Drive simulation of MBIST controllers and memory repair algorithms, Utilize EDA tools to validate DFT insertions and boundary scan logic, Bridge pre-silicon simulation with post-silicon testing for yield debug
Seniority
Staff, technical authority and cross-functional leadership
