ASIC DFT Technical Leader
Core
Lead DFT requirements and quality processes for next-generation networking chips from design cycle through post-silicon validation.
Role type
Senior IC ASIC DFT Technical Leader
Builds
Silicon One networking chips for Cisco core Switching, Routing, and Wireless products
Domain
Semiconductor / Networking Hardware
Required skills
DFT methodologies, JTAG protocols, Scan and BIST architectures, ATPG, EDA tools (TestMax, Tetramax, Tessent), Gate level simulation, Post-silicon validation, ATE patterns
Preferred skills
Verilog design, DFT CAD development, Test Static Timing Analysis, System Verilog, Functional verification
Technologies
VCS, TestMax, Tetramax, Tessent, P1687
Responsibilities
Collaborate with Front-end RTL and backend physical design teams to define DFT requirements early; Lead DFT and quality processes through Implementation flow and post-silicon validation; Participate in physical design signoff activities
Seniority
Senior, hands-on IC
