Senior Engineer-ASIC Design Verification
Core
Senior ASIC Design Verification Engineer responsible for IP/Block and sub-system verification from test plan creation to signoff.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Memory and storage solutions (DRAM, NAND, NOR) for data centers, AI, 5G, and mobile applications
Domain
Semiconductor / Memory and Storage / ASIC Design
Required skills
SystemVerilog/UVM, AMBA protocols (APB/AHB/AXI), RTL debugging, functional coverage coding, Verilog
Preferred skills
Mixed mode verification, mentoring junior engineers, cross-functional collaboration
Technologies
SystemVerilog, UVM, Verilog, AMBA
Responsibilities
Create test plans and develop UVM testbenches for IP/Block/sub-system verification; Ensure first-pass product through multi-dimensional verification coverage including mixed mode verification; Mentor and coach junior team members; Collaborate with domain specialists across geographical locations on core technical initiatives
Seniority
Senior, hands-on IC
