ASIC Verification Engineering

1,774 open positions

Principal DFT Design Engineer CadenceBANGALORE 2y Designing and implementing Design for Test (DFT) methodologies to enhance chip quality, reliability, and in-system test/debug capabilities.
SoC Design Verification Engineer MatXMountain View (HQ) or Remote $160k2y Deliver performant and functionally accurate silicon for high-performance GenAI products across compute, memory management, and high-speed connectivity.
Functional Modeling Engineer MediaTekBangalore 2y Develop and verify SystemC Functional / TLM models of components in automotive System-on-Chip (SoC) and provide stimulus and checkers for top-level virtual platform integration.
Lead Product Engineer - Design Verification (MM/VIP) CadenceAHMEDABAD, IN 2y Lead Product Engineer driving adoption of Cadence's Memory Verification IP (VIP) portfolio for protocols like DDR5, GDDR6, and DFI, supporting pre-sales and customer design flows.
Design Verification Engineer MediaTekBangalore 3y Architecting and developing testbenches and test-bench components for ISA, clock, reset, and power features of processors.
<Automotive>SoC Chip Design Engineer for DFT/DFM MediaTekHsinChu 3y Designing and implementing DFT/DFM methodologies for automotive ADAS SoC chips to ensure testability and manufacturability.
Design Verification Engineer MediaTekHsinChu 7y Developing and implementing verification plans for smartphone, TV, and ASIC product lines within the Mediatek chip development flow.
SoC Digital Verification Engineer, Multimedia Lab TikTokSan Jose, United States of America Develop and maintain automated verification environments and test plans for video codec hardware accelerators (FPGA/ASIC) to ensure functional and timing closure.
Senior SoC Digital Verification Engineer, Multimedia Lab TikTokSan Jose, United States of America Building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users.
芯片验证工程师 TencentBeijing, China End-to-end chip verification including module-level and system-level validation, environment setup, and quality assurance for SoC development.
DPU验证工程师-Data（上海） ByteDance上海 Build and maintain UVM verification environments for Data DPU chips, focusing on automation, reusability, and high-quality delivery of code and functional coverage.
SOC验证（CPU芯片） - 芯片研发 ByteDance北京 Build and maintain UVM verification environments for data center CPU chips, executing test plans covering performance, power, RTL/FW, and GTL simulations.
芯片验证工程师 TencentShenzhen, China End-to-end chip verification including module-level and system-level validation, environment setup, and test execution.
Rust SW-Silicon Co-verification Engineer MatXThis is a hybrid role that will require you to work from our Mountain View, CA o $120k Write Rust tests to verify software models and hardware design agree with each other and specifications, building test infrastructure and harnesses for chip verification.
芯片EVB板级PI/PPO验证工程师（芯片平台） - 芯片研发 ByteDance上海 End-to-end responsibility for post-silicon EVB board-level verification and chip productization mass production support for ByteDance's self-developed chips, ensuring verification quality.
芯片DFT工程师（芯片平台） - 芯片研发 ByteDance北京 Design and implement DFT solutions for SoC chips, covering scan, MBIST, ATPG, and boundary scan, while collaborating on timing/power-IR analysis and post-silicon ATE test debugging.
数字验证工程师（存算与AI） - 芯片研发 ByteDance北京 Design and verify high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and support large AI models.
EMU验证工程（存算与AI） - 芯片研发 ByteDance北京 Design and validate energy-efficient AI chips based on in-memory computing architectures to break the 'memory wall' bottleneck and support large AI models.
芯片验证工程师 TencentBeijing, China Develop verification strategies and environments, execute chip verification, and assist in debugging emulation and prototype issues for chip modules and architectures.
存储系统验证工程师（AI芯片） - 芯片研发 ByteDance北京 Front-end and back-end simulation verification for AI chip projects, focusing on coverage-driven verification and supporting hardware-software co-verification.
RTL Verification Engineer (On-site. Bengaluru, India) IxanaBengaluru, India Verify cutting-edge SoCs and IPs for AI-powered wearables using Wi-R, a patented non-radiative near-field communication technology.
ASIC验证工程师 ByteDance上海 Develops front-end and back-end verification for chip projects, creating verification plans, environments, and coverage analysis.
IP验证工程师-Data ByteDance上海 Develops and maintains verification environments and flows for self-developed IP cores, focusing on coverage-driven validation for frontend and backend chip projects.
SOC验证工程师 ByteDance上海 Develops and maintains verification environments and flows for SoC and system-level chip projects, focusing on front-end/back-end validation.

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