SOC Verification Engineer- SOC DDR, UMC
Core
SOC level verification engineer responsible for bringup verification of LPDDR5 and UMC at SOC, creating testbench collaterals, and coordinating with design teams.
Role type
Senior IC digital verification engineer (memory/SOC)
Builds
SOC testbenches, simulation infrastructure, and memory verification environments for LPDDR5/UMC
Domain
Semiconductor, SoC design, Memory verification
Required skills
SystemVerilog, UVM, C++, Python, SV assertions, Debug/triage, Coverage analysis, System bus protocols (AXI, PCIe, DDR, CHI, ACE), Verification methodologies, Make file flow, Boot up sequence
Preferred skills
LPDDR/UMC/Nand/Nor Flash expertise, IP/Subsystem/SOC verification, HW/SW co-verification, VCS/Verdi tools, UPF/CPF flows, JIRA
Technologies
VCS, Verdi, SystemVerilog, UVM, C++, Python, AXI, PCIe, DDR, CHI, ACE, UPF, CPF
Responsibilities
DDR Simulation bringup (TB, Testcase, coordination), Memory verification, Resolve simulation issues with memory architects
Seniority
Senior, hands-on IC
