Senior ASIC Design Verification Engineer - Slingshot
Core
Senior ASIC Design Verification Engineer responsible for pre-silicon verification, testbench development, and coverage closure for VLSI designs.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Pre-silicon verified ASIC designs for edge-to-cloud networking and storage systems
Domain
Semiconductor / VLSI Design / Networking
Required skills
SystemVerilog, UVM/OVM, Scoreboard development, Functional coverage analysis, Regression test management, Scripting (Python/Perl/Tcl), EDA tools, FPGA tools, Mentoring
Preferred skills
High-speed networking/NIC ASIC verification, Agentic AI coding tools, Linux development environments
Technologies
SystemVerilog, UVM, OVM, Python, Perl, Tcl, EDA tools, FPGA tools
Responsibilities
Develop SystemVerilog and UVM testbench components including bus functional models; Plan and implement block and integration level scoreboards; Write and analyze functional coverage; Triage regression failures and drive bug closure; Apply scripting and AI-assisted tools to improve verification speed and quality; Mentor less experienced staff.
Seniority
Senior, hands-on IC
