Lead DFT Engineer
Core
Lead DFT Engineer implementing and verifying DFT architecture, scan insertion, ATPG pattern generation, and test coverage analysis for cutting-edge processor designs.
Role type
Lead IC DFT Engineer
Builds
Front-end design and integration for Radeon GPUs and processors
Domain
Semiconductor / Hardware Design
Required skills
DFT architecture implementation, Scan insertion, ATPG pattern generation, Gate-level simulation, Test coverage analysis, IEEE1500, JTAG 1149.x, Memory BIST, Mentor testkompress, Synopsys Tetramax/DFTMAX, VCS simulation, Perl/Shell scripting, Verilog RTL design
Preferred skills
Senior silicon design collaboration, Post-silicon support, Yield learning
Technologies
VCS, Perl, Shell, Verilog, IEEE1500, JTAG 1149.x
Responsibilities
Implementation and verification of DFT architecture and features, Scan insertion and ATPG pattern generation, ATPG patterns verification with gate-level simulation, Test coverage and test cost reduction analysis, Post silicon support to ensure successful bring up and enhance yield learning
Seniority
Lead, hands-on IC
