Cellular Baseband Design Verification Intern
Core
Design Verification Intern for cellular baseband modems and RF link controllers in Apple's SoCs, ensuring quality and reliability of next-generation cellular systems.
Role type
Design Verification Intern (Silicon/ASIC)
Builds
Reusable UVM verification environments, coverage-driven test cases, and validation for complex IP and subsystem designs.
Domain
Semiconductor / Cellular Communications (4G/5G)
Required skills
Digital design fundamentals, SystemVerilog/Verilog, C/C++/Python programming, constrained-random testing, coverage-driven verification, test planning, RTL simulation, regression analysis, Python automation, LLM/ML tool exploration
Preferred skills
UVM, SystemVerilog Assertions (SVA), SystemC modeling, 3GPP physical layer knowledge, AHB/AXI/NoC protocols, embedded processor cores, prompt engineering
Technologies
UVM, SystemVerilog, Python, C/C++, SystemC, 3GPP, AHB, AXI, NoC, LLMs
