Senior CAD Engineer – Physical Verification
Core
Develop and maintain physical verification tools, flows, and methodologies for DRAM, HBM, NAND, and emerging memory products.
Role type
Senior IC physical verification engineer (CAD/EDA)
Builds
Physical verification rule decks (DRC/LVS) and automated verification flows for semiconductor memory chips
Domain
Semiconductor manufacturing / Physical Design Verification
Required skills
DRC and LVS physical verification, IC layout, process design rules, Python, SKILL, Tcl, Perl, C, C++, Linux/Unix, shell scripting, CMOS and VLSI fundamentals
Preferred skills
Calibre DRC/LVS rule decks in SVRF, nmDRC, nmLVS, RVE, layout-dependent effects, electrical rule checking (ERC), programmable ERC (PERC), antenna and density checks, rule-deck coverage optimization, Cadence Virtuoso, AI/ML in engineering workflows, source control, automated testing, release management
Technologies
Siemens Calibre, SVRF, nmDRC, nmLVS, RVE, Cadence Virtuoso, SKILL, Python, Tcl, Perl, C, C++, Linux/Unix
Responsibilities
Develop and debug Calibre DRC/LVS rule decks; translate process design rules into verification checks; partner with design and process teams on signoff strategies; guide design teams on verification methodologies and debugging; evaluate EDA technologies; automate verification setup and reporting; lead technical projects
Seniority
Senior, hands-on IC
