Senior Verification Engineer – High Speed Coherent Interconnect Hub
Core
Develop and verify High Speed Coherent Interconnect Hub IP for NVIDIA's next-generation multi-chip computing platforms.
Role type
Senior IC verification engineer (SoC/Interconnect)
Builds
High Speed Coherent Interconnect Hub IP for scalable, high-performance multi-chip computing platforms
Domain
Semiconductor / SoC Design / High-Speed Interconnects
Required skills
SystemVerilog, UVM, constrained-random verification, coverage-driven verification, RTL debugging, performance validation, scripting (Python/Perl/Shell)
Preferred skills
High-speed coherent interconnect verification (CHI, AXI), NoC experience, cache coherency knowledge, FPGA/emulation validation
Technologies
SystemVerilog, UVM, Python, Perl, Shell, FPGA, Emulation
Responsibilities
Develop and maintain verification infrastructure (testbenches, BFMs, checkers, monitors, scoreboards, assertions, constrained-random stimulus); Define and complete verification test plans for coherency protocol, ordering, error handling, and performance; Verify protocol compliance and interoperability across complex SoC and multi-chip interfaces; Develop and complete performance test plans to validate bandwidth, latency, QoS, and traffic management; Drive functional and code coverage closure for design signoff; Debug complex RTL and verification issues; Collaborate with FPGA, emulation, software, and post-silicon teams for system validation and silicon bring-up
Seniority
Senior, hands-on IC
