ASIC Verification Engineer
Core
Developing test benches and verification infrastructure for next-generation programmable ASICs used in high-speed packet forwarding and switching systems.
Role type
Senior IC ASIC verification engineer
Builds
ASICs for Cisco Nexus and ACI switching systems
Domain
Networking hardware / ASIC design
Required skills
System Verilog, UVM methodology, ASIC design flow, simulation, emulation, testbench construction (scoreboard, agents, sequencers, monitors), debugging
Preferred skills
C++, Python, Perl, TCL, shell scripting, high-speed Ethernet protocols
Technologies
System Verilog, UVM, OpenStack, Docker, Open vSwitch
Responsibilities
Designing UVM/SystemVerilog testbenches, defining new DV methodologies, enhancing existing testbenches, end-to-end verification of design blocks, top-level verification, emulation testing, ASIC bring-up
Seniority
Mid-level, hands-on IC
