ASICS Design Verification Engineer-Senior
Core
Develop comprehensive pre-silicon test planning, testbench development, coverage, assertion models, and formal verification for digital power IP within the ASIC verification lifecycle.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Digital power IP blocks for next-generation communication and data processing chips
Domain
Semiconductor / ASIC Design / Digital Verification
Required skills
SystemVerilog-UVM, Assertion Based Formal Verification, Perl/Python scripting, AMBA Bus protocols (AXI/AHB/APB), RTL design concepts, C/C++ programming
Preferred skills
Master's degree in CS/EE/CE, 6+ years ASIC verification experience, 6+ years digital design/RTL experience, 6+ years C/C++ experience, 6+ years block-level testbench development
Technologies
SystemVerilog, UVM, Perl, Python, AXI, AHB, APB, C, C++
