ASIC DFT Technical Leader || MBIST, SCAN , ATPG, Testmax, Tessent, Post Silicon Validation || Expereince - 11+ years
Core
Lead Design-for-Test (DFT) strategy and implementation for high-performance ASICs in Cisco's Silicon One architecture, driving quality from RTL through post-silicon validation.
Role type
Senior IC ASIC DFT Technical Lead
Builds
Next-generation networking chips (switching, routing, wireless)
Domain
Networking hardware / ASIC Design
Required skills
ATPG, Scan insertion, JTAG protocols (P1500, P1687), EDA tools (TestMax, Tetramax, Tessent), Gate-level simulation, Timing closure, Tcl/Python/Perl scripting, Post-silicon validation
Preferred skills
Verilog DFT logic development, DFT CAD development, Functional verification
Technologies
VCS, SDF, ATE, TestMax, Tetramax, Tessent
Responsibilities
Define DFT architecture and requirements early in the design cycle; Coordinate with RTL and physical design teams; Lead verification strategies and testing environments; Manage reusable code and infrastructure; Interface with vendors on timing closure and electrical planning; Perform verification and validation of first test vehicles.
Seniority
Senior, hands-on IC
