Design Verification Technical Lead
Core
Lead and manage a team responsible for hardware/firmware co-verification of embedded micro-processor subsystems and hardware accelerators in leading-edge SoCs.
Role type
Senior IC Technical Lead/Manager (ASIC Hardware/Firmware Co-Verification)
Builds
Security IP subsystems (cryptography, DMA, compression) for high-performance SoCs
Domain
Semiconductor / ASIC Design / Hardware Verification
Required skills
UVM System Verilog, C-DPI, FPGA prototyping, team leadership, performance modeling, test methodology design, SoC integration, AXI/AHB bus verification
Preferred skills
Firmware development, distributed team management, performance optimization, mentoring, complex problem analysis
Technologies
UVM, System Verilog, C-DPI, FPGA, AXI, AHB, UVC
Responsibilities
Lead high-performance engineering team, develop subsystem verification architecture and testbenches, execute hardware/firmware co-verification on FPGA prototypes, define IP-level DV APIs, drive verification metrics closure, support SoC integration and silicon bring-up
Seniority
Senior, hands-on IC with management responsibilities
