Design Verification Engineer
Core
Develop and execute verification plans, design simulation/co-emulation environments, and debug hardware/software DUTs for storage solutions.
Role type
Senior Design Verification Engineer (Hardware/Software)
Builds
Verification environments and testbenches for storage platforms
Domain
Semiconductor/Storage Hardware Design Verification
Required skills
SystemVerilog, UVM, RTL development (Verilog), C/C++, digital circuit design, code coverage analysis, Questa/Veloce platforms, storage protocols (UFS/USB/SAS/SATA)
Preferred skills
SystemC, commercial VIP integration
Technologies
Questa, Veloce, SystemVerilog, UVM, Verilog, C, C++, Perl, Shell, TCL
Responsibilities
Develop and execute verification plans including testbench architecture; Design and develop co-emulation and simulation-based verification environments; Integrate software and hardware DUTs; Implement and monitor code and functional coverage metrics; Debug complete testbenches on Questa and/or Veloce platforms; Mentor junior engineers on verification best practices.
Seniority
Senior, hands-on IC
