ASIC Verification Intern - Summer 2027
Core
Verification of memory subsystem components in Tegra SOCs for consumer graphics, self-driving cars, HPC, cloud computing, and AI.
Role type
ASIC Verification Intern
Builds
Memory subsystem components for Tegra SOCs
Domain
Semiconductor / ASIC Design
Required skills
RTL design, verification methodologies, debugging, computer architecture, logic design, algorithms, data structures
Preferred skills
Verilog, SystemVerilog, UVM, C, C++, Java, Python, Perl, memory controllers, DDR protocols
Technologies
Verilog, SystemVerilog, UVM, C, C++, Java, Python, Perl, Linux, Windows
Responsibilities
Develop comprehensive verification plans for design changes, collaborate with RTL engineers to debug failures and close coverage, perform dynamic simulations and formal verification, enable FPGA and software teams for testing, conduct post-silicon verification and debug
Seniority
Intern
