Senior Physical Verification Engineer
Core
Lead signoff-quality physical verification for advanced silicon programs, driving closure for complex designs to tapeout readiness.
Role type
Senior IC physical verification engineer
Builds
Tapeout-ready silicon designs
Domain
Semiconductor / ASIC physical design
Required skills
DRC, LVS, physical signoff methodology, tapeout flows, physical verification tools, foundry rule decks, complex issue debugging, scripting and automation
Preferred skills
Full-chip PV signoff at advanced nodes, reliability/density/fill/ERC checks, methodology improvement leadership
Technologies
DRC, LVS, physical verification tools, foundry rule decks
Responsibilities
Own physical verification closure for major blocks or full-chip designs; Lead debugging of complex DRC, LVS, and reliability-related issues; Define verification check plans, signoff criteria, and closure priorities; Partner with physical design, custom design, and CAD teams; Drive automation and methodology improvements; Review results and coach team members
Seniority
Senior, hands-on IC
