IC Verification Engineer
Core
Architect and develop scalable Testbench environments, drive test plans, and achieve full functional coverage for Block/Core/SOC features.
Role type
Senior IC verification engineer (ASIC)
Builds
Verification environments, test plans, and pseudo-random tests for complex digital designs
Domain
Semiconductor / ASIC Design
Required skills
System Verilog, UVM/VMM, Functional Coverage, Pseudo-random testing, Regression debugging, ASIC verification lifecycle, Complex protocol analysis
Preferred skills
PCIe protocol, AXI protocol, Makefiles
Responsibilities
Architect reusable Testbench environments, Drive test plans for Block/Core/SOC features, Build pseudo-random tests for functional coverage, Debug regression failures and analyze coverage gaps, Mentor junior team members, Lead verification strategy documentation and reviews
Seniority
Senior, hands-on IC
