SYSTEM VIRTUAL PLATFORM DEVELOPER
Core
Develop and integrate Transaction Level Models (TLMs) in SystemC/C++ to create virtual SoCs for pre-silicon software development and validation of 5G/6G network products.
Role type
Senior System Virtual Platform Engineer (SoC verification)
Builds
Virtual models and test environments for System-on-Chip (SoC) verification
Domain
Semiconductor / 5G and 6G telecommunications
Required skills
SystemC, C/C++, Object-Oriented Programming (OOP), Computer Architecture, Software Debugging, Build Systems (CMake/make), Toolchains (GCC), Scripting (Python/PERL), Simulation Infrastructure
Preferred skills
Embedded software design, RTL debugging, HW emulation/acceleration, Pre-silicon/post-silicon debug, AI/Agentic workflows, Engineering leadership
Technologies
SystemC, C++, CMake, GCC, Python, PERL, Git, Jenkins, Jira, GNU tools
Responsibilities
Develop and integrate TLMs based on hardware specifications; Design, develop, and debug test environments for virtual SoCs; Define test plans and coverage metrics; Execute hardware/software co-simulation and root-cause analysis; Collaborate with IP and system architects to translate requirements; Partner with IP teams to support RTL verification; Engage with EDA partners on virtual prototyping tools; Maintain and scale simulation infrastructure.
Seniority
Senior, hands-on IC
