Staff Digital Verification Engineer
Core
Staff Digital Design Verification Engineer owning verification of complex digital blocks and major SoC features for power management chips.
Role type
Staff Digital Design Verification Engineer
Builds
Power management SoCs for AI, datacenter, enterprise computing, networking, and high-performance power delivery
Domain
Semiconductor / Power Management ICs
Required skills
SystemVerilog, UVM, constrained random verification, functional coverage, SystemVerilog Assertions, RTL debug, Linux, Python/Bash/Perl/Tcl scripting
Preferred skills
SoC verification, embedded processor interfaces, PMBus/AVSBus/SVID/SVI3/I2C/SPI protocols, telemetry/fault handling, Cadence Xcelium/SimVision/Synopsys VCS/Verdi, formal verification, gate-level simulation
Technologies
SystemVerilog, UVM, Python, Bash, Perl, Tcl, Cadence Xcelium, SimVision, vManager, JasperGold, Synopsys VCS, Verdi
Responsibilities
Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure; Develop feature-based verification plans; Build and extend reusable SystemVerilog/UVM environments; Develop constrained random and targeted tests; Drive functional, code, toggle, FSM, and assertion coverage closure; Debug RTL, testbench, assertion, integration, and regression failures; Automate regression, triage, reporting, and analysis workflows; Communicate status, risks, dependencies, and closure evidence
Seniority
Staff, hands-on IC with technical leadership
