Digital Design Engineer
Core
Architecture, RTL design, and integration of PHY IP blocks for SerDes and high-speed interface IP within SoCs.
Role type
Digital Design Engineer (SerDes/High-Speed Interface IP)
Builds
PHY IP blocks for System-on-Chip (SoC)
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design, PHY IP architecture, front-end/back-end integration, cross-functional collaboration, system-level IP verification, mixed-signal integration
Responsibilities
Develop and implement RTL code for PHY IPs focusing on performance, power efficiency, and silicon area optimization; Handle integration of PHY IPs in front-end and back-end design flows; Work with MAC design and Design Verification teams for system-level IP verification; Collaborate with analog design teams for PHY/SerDes co-simulation and mixed-signal integration
