Principal Physical Design Engineer (RTL-to-GDSII)
Core
Lead full-flow physical design implementation for massive, high-speed blocks and SoCs, transforming RTL into GDSII while optimizing PPA and eliminating systemic bottlenecks.
Role type
Principal Physical Design Engineer (RTL-to-GDSII)
Builds
High-performance silicon for edge-to-cloud AI computing systems
Domain
Semiconductor design, sub-5nm nodes, AI hardware
Required skills
Full-flow physical design ownership, PPA optimization, sub-5nm physics expertise, Static Timing Analysis, Physical Verification, Power Integrity, ECO methodology, Tcl scripting, Python scripting
Preferred skills
First principles thinking, cross-functional collaboration, mentorship, automated flow development
Technologies
Cadence Innovus, Tempus, Joules, Pegasus, Voltus
Responsibilities
Lead implementation of massive blocks/SoCs from Synthesis through Sign-off; Analyze and optimize interplay between library cells, metal stacks, and tool engines; Build and refine robust, repeatable execution methodologies; Collaborate with RTL, Architecture, and DFT teams to influence early design decisions; Identify and architect automated solutions for pipeline bottlenecks
Seniority
Principal, hands-on IC with mentorship
