Principal Digital Design Engineer
Core
Lead digital design architecture, RTL, low power design, synthesis, and timing analysis for power management chips serving consumer, industrial, and automotive applications.
Role type
Principal Digital Design Engineer (Power Management ICs)
Builds
Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches, and efuses
Domain
Semiconductor / Power Electronics / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital RTL design, Low power design, Synthesis and timing analysis, System Verilog (assertion), CDC analysis, P&R, UPF, Verilog, TCL, Perl, Python, XML, Digital architecture trade-offs, Pre-silicon platform bring-up (SOCV, Emulation, FPGA), Post-silicon validation
Preferred skills
Knowledge of MCU systems, Development of digital control peripherals, Experience with Constant-on-time/Peak/Valley Current/Voltage Mode control mechanisms, Hysteretic/Multi-Phase Controllers, Smart Power Stages
Technologies
Verilog, System Verilog, TCL, Perl, Python, XML, SOCV, FPGA, UPF
Responsibilities
Lead digital design architecture from micro-architecture to RTL implementation, Execute tool flows for IP quality control, Support bring-up of features on pre-silicon platforms, Own technical outcome of design and verification, Identify and implement new systems/tools to improve design processes, Support post-silicon validation activities
Seniority
Principal, hands-on IC design and architecture leadership