Sr Principal Digital Design Engineer
Core
Sr. Principal Digital Design Engineer developing Power Management ICs (LED drivers, SiC drivers, smart-Switches, efuses) for consumer, industrial, and automotive applications.
Role type
Sr. Principal Digital Design Engineer (SoC RTL implementation)
Builds
Power management chips (LED/SiC/smartFET/Efuse drivers) and SoC digital controls
Domain
Semiconductor / Power Management / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design, digital design architecture, synthesis, timing analysis, low power design, system Verilog, UPF, CDC, Verilog, TCL, Perl, Python, XML, micro-architecture definition, pre-silicon bring-up (SOCV, Emulation, FPGA), post-silicon validation, peripheral integration (I2C, SPI, LIN, CAN)
Preferred skills
Experience with microprocessor interconnects, complex control loops, failure analysis, cross-functional collaboration
Technologies
Verilog, TCL, Perl, Python, XML, SOCV, Emulation, FPGA, I2C, SPI, LIN, CAN
Responsibilities
Implement micro-architecture to RTL for power driver digital controls; Support feature bring-up on pre-silicon platforms; Own technical outcome of design and verification; Lead and support customer/production issues and failure analysis; Support post-silicon validation; Execute project milestones and report progress.
Seniority
Sr. Principal, hands-on IC design & architecture