Senior Physical Design Engineer
Core
Lead physical implementation of complex silicon blocks from synthesis to sign-off, optimizing Power, Performance, and Area (PPA) for edge-to-cloud AI hardware.
Role type
Senior Physical Design Engineer (IC)
Builds
Custom AI accelerator chips for power, energy, and space-constrained applications
Domain
Semiconductor / Hardware / AI Systems
Deliverable
production ML models | product features
Required skills
Physical Design (Floor-planning, Placement, CTS, Routing), PPA Optimization, Static Timing Analysis (STA), DRC/LVS/ERC Verification, Tcl scripting, Python automation
Preferred skills
Experience with Cadence Innovus/Tempus, debugging tool failures, left-shifting physical constraints
Technologies
Cadence Innovus, Cadence Tempus, Tcl, Python
Responsibilities
Lead physical implementation of complex blocks from Synthesis through to CTS, Routing, and Sign-off; Optimize PPA through deep-dive analysis of timing paths, power profiles, and congestion; Automate repetitive tasks and build custom analysis scripts using Tcl and Python; Resolve complex DRC/LVS, IR drop, and timing violations independently; Collaborate with RTL and DFT teams to optimize designs for routing and timing from the start
Seniority
Senior, hands-on IC