Sr Principal Design Engineer
Core
Owns full DFT lifecycle for high-speed, low-power chip designs, defining test architecture and implementing RTL changes to ensure testability and timing closure.
Role type
Sr Principal Design Engineer (DFT)
Builds
Production silicon chips with embedded DFT infrastructure
Domain
Semiconductor / Electronic Design Automation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture definition, RTL modification for DFT, scan insertion, LEC, low power CLP, timing constraints for test mode, ATPG, boundary scan, ACJTAG, IEEE 1500, IEEE 1687 (iJTAG), zero delay/timing simulation, post-silicon bring-up support
Preferred skills
Experience with very high speed and low power designs
Technologies
IEEE 1500, IEEE 1687, ACJTAG, ATPG, LEC, CLP
Responsibilities
Define test architecture, implement RTL changes for DFT, perform scan insertion and LEC checks, develop timing constraints for test mode, execute zero delay and timing simulations, support post-silicon bring-up, interact with customers on DFT aspects
Seniority
Sr Principal, hands-on IC
