STA Synthesis Engineer
Core
Own timing constraints and drive timing closure for image sensor full chip and sub-system levels, including pre/post-layout analysis and ECO generation.
Role type
Senior IC STA Synthesis Engineer
Builds
Image sensor SoCs and subsystems
Domain
Semiconductor / ASIC Design / Image Sensors
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
STA fundamentals, AOCV/POCV, signal integrity, cross-talk noise, process variation, timing ECO generation, timing constraint development (hierarchical/flat), timing constraint validation, pre/post-layout timing analysis, timing convergence, UPF basics, power optimization techniques, ASIC Back End flows, automation scripting (TCL, Python, Perl)
Preferred skills
UPF based static low power check, power analysis
Technologies
PrimeTime, Tempus, EDA tools
Responsibilities
Develop and release timing constraints for synthesis/PD work, analyze and debug pre-layout and post-layout timing reports, drive timing closure at sub-system and full chip levels, perform RTL PPA analysis for power/performance/area trade-offs, develop automation scripts for efficiency improvement
Seniority
Mid-Senior, hands-on IC
