Design Engineer
Core
Physical implementation of high-performance custom CMOS ASICs for AI, Cellular, Networking, Computing, and Storage products.
Role type
Senior IC physical design engineer
Builds
High-performance SoC designs operating at speeds exceeding 1 GHz
Domain
Semiconductor / VLSI / ASIC
Deliverable
production ML models | product features | infrastructure
Required skills
VLSI design, CMOS logic, digital circuit fundamentals, floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification (DRC/LVS), UNIX/Linux, TCL
Preferred skills
Python, Perl, Cadence Innovus, Synopsys ICC2, PrimeTime, power planning, IR/EM checks, post-route optimization
Technologies
Cadence Innovus, Synopsys ICC2, PrimeTime, UNIX/Linux
Responsibilities
Contribute to physical design implementation of large-scale ASICs, support floorplanning, placement, clock tree synthesis, routing, and timing closure, collaborate on block-level integration and design signoff, utilize EDA tools for design and verification, contribute to design flow improvements and automation, assist in timing analysis and power planning, interface with customers and internal stakeholders
Seniority
Mid-level, hands-on IC