Senior Digital Design Engineer
Core
Architecting, designing, and integrating PHY IP blocks for high-speed interfaces within System-on-Chip (SoC) solutions.
Role type
Senior Digital Design Engineer (SerDes/High-Speed Interface IP)
Builds
High-performance PHY IP blocks for Ethernet SerDes, USB, PCIe, HDMI, DisplayPort, MPHY, and CPHY
Domain
Semiconductor / SoC Design / High-Speed Interface
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design, PHY IP architecture, front-end and back-end integration, SoC connectivity, performance optimization, power efficiency, silicon area optimization
Preferred skills
Cross-functional collaboration with MAC design and Design Verification (DV) teams, analog design co-simulation, mixed-signal integration
Technologies
Ethernet SerDes, USB, PCIe, HDMI, DisplayPort, MPHY, CPHY
Responsibilities
Contribute to the architectural design of PHY IPs for high-speed interfaces; Develop and implement RTL code for PHY IPs with a focus on performance, power efficiency, and silicon area optimization; Handle the integration of PHY IPs in both front-end and back-end design flows; Work closely with MAC design and Design Verification (DV) teams for system-level IP verification; Collaborate with analog design teams for PHY/SerDes co-simulation and mixed-signal integration
Seniority
Senior, hands-on IC
