Senior Physical Design Engineer - Signoff Methodology
Core
Develop and refine backend methodologies and flows from RTL to GDS, focusing on signoff disciplines for high-quality VLSI designs.
Role type
Senior IC physical design engineer (backend methodology)
Builds
High-performance, large-scale, and complex silicon devices
Domain
Semiconductor / VLSI / Chip Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL to GDS flow development, Physical Synthesis, Place and Route (PnR), Static Timing Analysis (STA), Physical Verification (PV), Formal Verification (FV), Backend design experience
Preferred skills
Physical Design CAD, Synopsys tools, Cadence tools
Technologies
Synopsys, Cadence, EDA tools
Responsibilities
Develop and improve flows for all signoff disciplines, Contribute to the evolution of implementation tool flows, Collaborate with engineering teams to enhance implementation tool flows, Work with advanced silicon technologies and processes
Seniority
Senior, hands-on IC
