DSP Firmware Engineer
Core
Design, simulate, implement, and validate DSP ASICs for coherent optical transmission in fiber networks.
Role type
Senior RTL Design Engineer (DSP ASIC)
Builds
High-performance integrated circuits for coherent DSP devices
Domain
Semiconductor / Optical Communications / ASIC Design
Deliverable
product features
Required skills
RTL design (Verilog/SystemVerilog), digital logic design, synchronous design principles, hardware state machines, simulation environments, debugging tools
Preferred skills
On-chip bus protocols (AMBA AXI/AHB/APB), microprocessor core integration, ASIC design flows, synthesis, static timing analysis
Technologies
Verilog, SystemVerilog, ModelSim, VCS, Questa
Responsibilities
Develop RTL for microcontroller subsystems, design on-chip buses and memory interfaces, create block-level specifications, collaborate with verification teams, support synthesis and timing closure, participate in design reviews
Seniority
Mid-Senior, hands-on IC
