DSP Firmware Engineer
Core
Design and implement RTL for microcontroller subsystems, on-chip buses, memory interfaces, and peripherals for high-performance coherent DSP ASICs used in fiber optical networks.
Role type
Senior IC digital design engineer (RTL)
Builds
Coherent DSP ASICs for hyper-scale and telecom networks
Domain
Semiconductor / Digital IC Design
Required skills
RTL design (Verilog/SystemVerilog), digital logic design, synchronous design principles, hardware state machines, simulation environments (ModelSim/VCS/Questa), block-level specification
Preferred skills
On-chip bus protocols (AMBA AXI/AHB/APB), microprocessor core integration, ASIC design flows (synthesis/timing analysis)
Technologies
Verilog, SystemVerilog, ModelSim, VCS, Questa, AMBA AXI, AMBA AHB, AMBA APB
Responsibilities
Develop RTL for microcontroller subsystems, design on-chip buses and memory interfaces, create block-level specifications, collaborate with verification teams on test plans and debugging, support synthesis and timing closure teams, participate in design reviews
Seniority
Mid-Senior, hands-on IC
