Principal Engineer, STA & Synthesis
Core
Own synthesis and timing closure sign-off for low-power, chiplet-based MCU designs on cost-optimized mature process nodes.
Role type
Principal Engineer, ASIC/SoC Implementation Lead
Builds
Low-power, chiplet-based MCU designs for automotive, industrial, infrastructure, and IoT markets
Domain
Semiconductor, ASIC/SoC Design, Low-Power Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-gate synthesis, Static Timing Analysis (STA), timing closure, multi-mode/multi-corner analysis, UPF/CPF power intent, ECO flows, scripting (Tcl/Perl/Python), hierarchical timing closure, external interface timing (SPI/I2C/Ethernet/CAN)
Preferred skills
chiplet-based design timing sign-off
Technologies
Synopsys, Cadence, 22nm, 12nm, UPF, CPF
Responsibilities
Drive RTL-to-gate synthesis for complex multi-die MCU designs, optimize for timing/power/area, lead STA and timing closure across corners/modes, ensure sign-off compliance, resolve timing issues with RTL/DFT/physical design teams, define synthesis/timing methodologies, evaluate EDA tools/flows
Seniority
Principal, hands-on IC
