Physical Design Engineer
Core
Own planning, execution, and closure of complex digital blocks, managing floorplanning, placement, CTS, routing, and timing closure to ensure signoff readiness.
Role type
Physical Design Engineer
Builds
Digital logic blocks for semiconductor chips
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cadence Innovus, timing closure (Setup/Hold, MMMC), congestion debugging, DRC/LVS signoff, SI-aware optimization, macro placement, pin access management, blockage resolution, density management
Technologies
Cadence Innovus
Responsibilities
Drive block-level floorplanning, placement, CTS, routing, and ECO closure; Lead timing closure including Setup/Hold, MMMC, constraints, and QoR improvement; Debug congestion and routability issues; Ensure block signoff readiness via DRC/LVS and IR/EM closure; Coordinate with STA, DFT, Synthesis, and CAD teams for tapeout execution