Principal ASIC Design Engineer
Core
Lead the micro-architecture, implementation, and verification of a digital sub-system within the Treo platform, a high-performance analog and mixed-signal solution for automotive, medical, industrial, and AI data center markets.
Role type
Principal ASIC Design Engineer (Digital Sub-System Lead)
Builds
Digital sub-systems for the Treo platform (65nm BCD technology) supporting 1–90V voltage ranges and 175°C operating temperatures.
Domain
Semiconductor design (ASIC), Automotive, Industrial, AI Data Centers
Deliverable
production ML models | product features
Required skills
SoC architecture, IP selection, RTL design and verification, FSMs, timing analysis, Verilog/System Verilog, Lint, CDC, RDC, Design Compiler, APB/AHB/AXI/SPI/I2C/DMA interfaces, pipelining, low latency, power optimization, DFT, Functional Safety (FuSa), Python, PERL
Preferred skills
AI-driven digital design tools, platform standardization, IP reuse strategies
Technologies
65nm BCD, Verilog, System Verilog, Python, PERL, Lint, CDC, RDC, Design Compiler
Responsibilities
Micro architect, implement and verify the digital Sub-System; Lead design and verification planning and ensure design testability; Perform hands-on RTL coding and scripting for any automation; Ensure the IP meets the ASIL requirements; Drive innovation and standardization.
Seniority
Principal, hands-on IC with leadership
