Principal Design Engineer
Core
Designing high-performance physical IP for industry-standard protocols, covering digital architecture, RTL, low-power design, and synthesis for SerDes portfolios.
Role type
Principal Design Engineer (Digital/Physical IP)
Builds
High-performance SerDes physical IP for industry-standard protocols
Domain
Semiconductor / Digital Design / Physical Layer
Required skills
Digital architecture, RTL implementation, low-power design, synthesis, timing analysis, behavioral coding, constraint generation, power management, DFT, verification strategy, embedded uC design, Serial standards (PCIe, USB, Ethernet)
Preferred skills
Mixed-signal design, scripting of design automation, debugging verification test cases/SVA, multiple programming languages (System Verilog, Python, C/C++)
Technologies
System Verilog, Python, C/C++, Perforce, Git, SVN
Responsibilities
Drive architecture from micro-architecture to RTL implementation, execute tool flows for IP quality control, collaborate with verification and analog teams, specify coverage points and testing strategies
Seniority
Principal, hands-on IC
