Principal ASIC / RTL Design Engineer
Core
Leading digital design architecture and RTL implementation for power management ICs including DC-DC PMIC, multiphase controllers, and SiC drivers.
Role type
Principal ASIC / RTL Design Engineer
Builds
Power management products for consumer, industrial, and automotive applications
Domain
Semiconductor / Power Management
Deliverable
production ML models | product features | infrastructure
Required skills
Digital design architecture, RTL design, low power design, synthesis and timing analysis, Physical Design interface, RTL2GDS flows, System Verilog assertions, CDC analysis, P&R, UPF, Verilog, TCL, Perl/Python/XML programming, platform-based development
Preferred skills
Experience leading Digital Design and ASIC/Mixed signal chip developments, understanding of end-to-end digital design flow
Technologies
System Verilog, Verilog, TCL, Perl, Python, XML, RTL2GDS
Responsibilities
Deploy platform front end tool flow, implement micro-architecture to RTL implementation, work with methodology development teams to establish development methods and coding processes, collaborate with cross-functional teams for seamless integration
Seniority
Principal, hands-on IC with leadership