Staff Digital Design Engineer
Core
Lead digital design architecture, RTL, low power design, synthesis, and timing analysis for power management chips including DC-DC PMIC, multiphase controllers, and LED drivers.
Role type
Staff Digital Design Engineer (Power Management ICs)
Builds
Power management products for consumer, industrial, and automotive applications
Domain
Semiconductor / Power Electronics
Deliverable
production ML models | product features
Required skills
Digital RTL design, ASIC synthesis, timing analysis, CDC, UPF, System Verilog, Verilog, TCL, Perl, Python, XML, Multi-phase controller topologies, Digital architecture trade-offs
Preferred skills
Pre-silicon platform bring-up (SOCV, Emulation, FPGA), Post-silicon validation, Tool flow development, Process improvement
Technologies
Verilog, TCL, Perl, Python, XML, SOCV, FPGA, UPF
Responsibilities
Lead digital design architecture and RTL implementation, Drive micro-architecture to RTL, Support system-level feature bring-up on pre-silicon platforms, Own technical outcome of design and verification, Identify and implement new design tools and processes, Support post-silicon validation
Seniority
Staff, hands-on IC with architectural leadership